This invention relates to electronic circuitry and, more particularly, to a MOS circuit for driving an ECL circuit.
FIG. 1 is a block diagram of a portion of a conventional computing system 10. Computing system 10 comprises a central processing unit (CPU) 14 for processing instructions and data, a cache memory 18 for storing pages of data for high speed access by CPU 14, and a floating point unit (FPU) 22 for performing arithmetic operations on floating point data from cache memory 18. CPU 14 communicates data to cache memory 18 over a CPU-cache bus 26 and receives data from cache memory 18 over a cache-CPU bus 30. FPU 22 also receives data from cache memory 18 over a cache-FPU bus 34 which is coupled to cache-CPU bus 30. CPU 14 communicates with FPU 22 over a CPU-FPU bus 38.
Since cache memory 18 is intended to provide high speed access to data, it should be constructed with circuit elements which respond quickly to the signals used to access the data. Emitter coupled logic (ECL) circuits often meet the performance requirements of such high speed applications, so they are often used in cache memory designs. FIG. 2 is a schematic diagram of a conventional ECL gate 42 which may be used alone or in conjunction with other circuitry to meet the needs of a particular high speed circuit. ECL gate 42 comprises a first bipolar transistor 46 and a second bipolar transistor 50. Emitters 52, 54 of transistors 46 and 50 are coupled together and through a resistor R3 to a ground potential. A collector 62 of transistor 46 is coupled to a voltage (and current) source V.sub.CC through a resistor R1. Similarly, a collector 66 of transistor 50 is coupled to V.sub.CC through a resistor R2. A base terminal 70 of transistor 50 is coupled to a reference voltage V.sub.REF, and a base terminal 74 of transistor 46 is coupled to a control input voltage V.sub.IN. In a differential ECL gate receiving a differential input voltage, the reference voltage V.sub.REF is the complement of the input voltage V.sub.IN.
ECL gate 42 is controlled so that current always flows from V.sub.CC, through transistor 46 or 50, and to ground. Which transistor 46 or 50 conducts the current depends upon the magnitude of V.sub.IN relative to V.sub.REF. If V.sub.IN is positive relative to V.sub.REF, then current flows through transistor 46, and if V.sub.REF is positive relative to V.sub.IN, then current flows through transistor 50.
Current flow through either transistor 46 or transistor 50 causes a voltage drop of approximately 0.6 volts across resistors R1 or R2, respectively. For example, when current flows through transistor 46, the voltage at collector 62 is approximately V.sub.CC -0.6 volts. Consequently, when V.sub.IN equals V.sub.CC -0.6 volts, transistor 46 is on the edge of saturation. If V.sub.IN is greater than V.sub.CC -0.6 volts, then transistor 46 is saturated, the base is forward biased with respect to the collector, and extra charge is stored in the base. Unfortunately, when a signal is supplied to the base terminal of a saturated transistor to turn the transistor off, the extra charge in the base must be dissipated before the transistor can turn off, and the delay may be unacceptable. Therefore, the driving circuit should prevent saturation by keeping V.sub.IN from going more positive than V.sub.CC -0.6 volts. In a typical ECL circuit, V.sub.CC equals 0 volts and ground equals -5 volts. Thus, V.sub.IN should not be greater (more positive) than -0.6 volts.
In the computing circuit shown in FIG. 1, CPU 14 may be constructed with metal oxide semiconductor (MOS) circuit elements. FIG. 3 is a schematic diagram of a MOS circuit 80 for driving one or more ECL gates 42 shown generally as an ECL circuit 84. ECL circuit 84 may be a part of cache memory 18. MOS driver 80 includes PMOS transistors Q1, Q2, Q3, and Q4. Transistor Q1 has a gate terminal 88, a current flowing terminal 90, and a current flowing terminal 92. Similarly, transistor Q2 includes a gate terminal 94, a current flowing terminal 96, and a current flowing terminal 98. The current flowing terminal 92 of transistor Q1 is coupled to the current flowing terminal 98 of transistor Q2 at a first voltage node 100. First voltage node 100 is coupled to a voltage (and current) source V.sub.CC through a line 102. Gate terminal 88 of transistor Q1 is coupled for receiving control signals applied to a line 104 through inverters 106, 108, 110, and 112. Gate terminal 94 of transistor Q2 receives the control signals applied to line 104 through inverters 106, 114 and 116. The signal applied to gate terminal 88 is thus an inverted copy of the signal applied to gate terminal 94.
Transistor Q3 has a gate terminal 120, a current flowing terminal 124, and a current flowing terminal 128. Similarly, transistor Q4 has a gate terminal 130, a current flowing terminal 134, and an current flowing terminal 138. Current flowing terminal 128 of transistor Q3 is coupled to current flowing terminal 90 of transistor Q1 at a node 139. Similarly, current flowing terminal 1 38 of transistor Q4 is coupled to current flowing terminal 96 of transistor Q2 at a node 142. Current flowing terminals 124 and 134 are coupled together at a second voltage node 150 which, in turn, is coupled to a voltage V.sub.CC -2.0 volts through a line 154. Gate terminal 120 of transistor Q3 receives the control signals applied to line 104 through inverters 106, 160, and 164. Gate terminal 130 of transistor Q4 receives the control signals applied to line 104 through inverters 106, 166, 170, and 174.
A transmission line T1 is coupled to node 142 and to the true input terminal of differential ECL circuit 84, whereas a second transmission line T2 is coupled to node 139 and to the complement input terminal of differential ECL circuit 84. The signals at nodes N1 and N2 may be used as the true and complement V.sub.IN signals for ECL gates 42 in ECL circuit 84. A terminating resistor R.sub.T is coupled between transmission line T1 and transmission line T2 for preventing reflections along transmission line T1 or transmission line T2. If the transmission lines have an impedance of 50 ohms, the correct value for R.sub.T to prevent reflections is 100 ohms, and this value will be assumed hereafter. Separate terminating resistors of 50 ohms (not shown) for each transmission line are sometimes used for this purpose as well.
In operation, either transistors Q1 and Q4 or transistors Q2 and Q3 are conducting at any given time. When transistors Q1 and Q4 are conducting, current flows along line 102, through transistor Q1, through transmission line T2, through termination resistor R.sub.T, through transmission line T1, through transistor Q4, and through line 154. When transistors Q2 and Q3 are conducting, then current flows through line 102, through transistor Q2, through transmission line T1, through termination resistor R.sub.T, through transmission line T2, through transistor Q3, and through line 154. In any event, current always flows through line 102, through node 100, to node 150, and through line 154, and complementary output signals appear at nodes 139 and 142.
FIG. 4 is a schematic diagram showing a resistor circuit 180 that is the equivalent of circuit 80 shown in FIG. 3. A resistor RQ.sub.12 represents the resistance through either transistor Q1 or transistor Q2, depending on which transistor is conducting at the time. Similarly, a resistor RQ.sub.34 represents the resistance through either transistor Q3 or transistor Q4, again depending upon which transistor is conducting. Given a voltage of V.sub.CC at the upper portion of the circuit and a voltage of V.sub.CC -2 volts at the lower portion of the circuit, then the voltage drop across the series of resistances is equal to -2 volts. To limit the voltage at node N1 to V.sub.CC -0.6 volts (to avoid saturating the ECL transistors as discussed above), and assuming RQ.sub.12 equals R.sub.34 equals R, then the required resistance of transistors Q1-Q4 may be determined by solving the equation R/(2R+100).times.(-2) volts=-6 volts. That is, the resistance R of each transistor Q1-Q4 should be 75 ohms or greater.
It is common for the resistance of transistors to vary by up to a factor of 4, depending on operating voltage, temperature, process variations during manufacture, etc. Thus, a transistor having a minimum resistance of 75 ohms, to satisfy the maximum 0.6 volt requirement, may have a maximum resistance of 300 ohms. Such a resistance still satisfies the -0.6 volt limitation at node N1, but then the total voltage swing across resistor R.sub.T is only approximately 0.28 volts, which provides a very weak differential signal across nodes N1 and N2. A desirable voltage swing is approximately 0.6 volts or more. If the transistors are designed to provide a 0.6 volt swing when the transistors are weak (high resistance), then, when the transistors are strong (low resistance) the voltage at node N1 would rise above the -0.6 volt maximum, thus saturating the ECL transistors.